1. Technical Field
The present disclosure relates to nonvolatile memories and more particularly to a sense amplifier for reading nonvolatile memory cells.
2. Description of the Related Art
Sense amplifiers are conventionally used to sense a conductivity state of non-volatile memory cells, which can generally be a high conductivity state or a low conductivity state, and to output a data signal that is a function of the state of the memory cell. For example, electrically erasable and programmable memory cells can be in a programmed state or in an erased state, which correspond to two different conductivities.
Sense amplifiers may be single-ended or differential. Single-ended sense amplifiers have an internal current source or voltage source to sense, via a single sense input, the state of a memory cell. Differential sense amplifiers have two sense inputs. FIG. 1 shows an example of a conventional differential sense amplifier SA1, of the type disclosed in U.S. Pat. No. 5,764,572. Sense amplifier SA1 has a first sense input SI1 and a second sense input SI2. The first sense input SI1 is linked to a memory cell MC through a bitline BL1. The second sense input SI2 is connected to a reference line BL2 linked to a current source CS or to any other reference element such as a reference resistor.
Sense amplifier SA1 comprises a latch LT1 comprising two cross-coupled inverting gates IV1, IV2, each comprising one p-channel transistor T1, T11 and one re-channel transistor T2, T12, respectively. The output of gate IV1 and the input of gate IV2 are connected to a first input/output node IO1, and the output of gate IV2 and the input of gate IV1 are connected to a second input/output node IO2. Node IO1 supplies data signal D and node IO2 supplies inverted data signal /D.
Node IO1 is also linked to the first sense input SI1 through p-channel and re-channel isolation transistors T3, T4 arranged in parallel, and an n-channel cascode transistor T6. Node IO2 is also linked to the second sense input SI2 through p-channel and n-channel isolation transistors T13, T14 arranged in parallel, and an n-channel cascode transistor T16. Isolation transistors T3, T13 are controlled by a signal IS, and isolation transistors T4, T14 are controlled by an inverted signal /IS. The cascode transistors T6, T16 are controlled by a voltage Vcsc.
Sense amplifier SA1 also comprises p-channel precharge transistors T5, T15 controlled by a precharge signal PRE, whose drain terminals (D) are respectively connected to the drain terminal (D) of transistor T6 and the drain terminal (D) of the transistor T16.
The reading of memory cell MC comprises a precharge phase and a read phase. During the precharge phase, the first and second sense inputs are brought to a precharge voltage Vpre by means of transistors T5, T15 and through the cascode transistors T6, T16. A voltage Vcc is applied on the source terminals (S) of transistors T1, T11 of the latch LT1 while a signal ACT is applied on the source terminals (S) of transistors T2, T12. During the precharge phase, signal ACT is set to voltage Vcc, thereby maintaining transistors T2, T12 in the OFF state.
Once voltage Vpre has been reached on bitline BL1 and on reference line BL2, the precharge signal PRE is pulled high and the reading of the memory cell MC starts. The voltages present on the first and second sense inputs SI1, SI2 begin to decrease at different rates, creating a voltage difference that depends on whether the memory cell is in the high or low conductivity state. If the memory cell is in the high conductivity state, the voltage present on the bitline BL1 drops more quickly than that on the reference line BL2. If the memory cell is in the low conductivity state, the voltage present on the bitline BL1 drops more slowly than that on the reference line BL2. The voltage difference between the bitline and the reference line is amplified by the cascode transistors T6, T16 and an amplified voltage difference appears between nodes IO1, IO2 of the latch.
Transistors T3, T4, T13, T14 are then deactivated, thereby disconnecting nodes IO1, IO2 from the sense inputs SI1, SI2, and the latch is fully activated by setting signal ACT to zero. The amplified voltage difference between nodes IO1, IO2 forces the latch into one of its two possible stable states, and sense amplifier SA1 outputs a data signal D=0 or D=1 corresponding to the conductivity state of the memory cell.
Such a conventional sense amplifier may have some drawbacks according to the conditions in which it is used or implemented. In particular, the n-channel isolation transistors T4, T14 must be quite large and, in low voltage integrated circuits, must be driven by a boosted voltage /IS supplied by a charge pump since they are arranged in the precharge path. Therefore, a significant amount of power may be consumed when switching them with a charge pump due to charge pump efficiency problems.
In addition, when such a sense amplifier SA1 is implemented in integrated circuits using low power supply, it may happen that the latch LT1 remains in a “metastable” state (i.e., neither 1 nor 0), thereby outputting a corrupted data signal. In particular, such a problem may arise in integrated circuits powered by a voltage Vcc of less than 1.8 V, for example those manufactured according to the 180 nanometer CMOS process.
Therefore, it may be desired to provide a low power sense amplifier optimized for low voltage memory chips.